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? semiconductor MSM7603/7603b 1/20 ? semiconductor MSM7603/7603b echo canceler general description the MSM7603/7603b is an improved version of the msm7602 with basically the same configuration, and offers twice the cancelable echo delay time of the msm7602. the MSM7603b i/o interface allows switching between m -law pcm and a-law pcm. the MSM7603/7603b is a low-power cmos ic device for canceling echo (in an acoustic system or telephone line) generated in a speech path. echo is canceled, in digital signal processing, by estimating the echo path and generating a pseudo echo signal. when used as an acoustic echo canceler, the device can cancel the acoustic echo, between the loud speaker and the microphone, which occur during hands free communication such as on a cellular phone or a conference system phone. when used as a line echo canceler, the device can cancel the line echo which returns due to impedance mismatching in a hybrid. in addition, a quality conversation is made possible by controlling the level and by preventing howling through a howling detector, double talk detector, attenuation function and a gain control function, and by controlling the low level noise by means of a center clipping function. the use of a single chip codec, such as the msm7704 (3 v) and msm7533 (5 v), allows an economic and efficient echo canceler to be configured. features ? can handle both acoustic and telephone line echoes. ? switchable between m -law pcm and a-law pcm interfaces. (MSM7603b) ? cancelable echo delay time: MSM7603b-003 .............. 55 ms (max.) ? echo attenuation : 30 db (typ.) ? clock frequency : 19.2 mhz 17.5 mhz to 20 mhz (when internal sync signal not used) ? power supply voltage : 2.7 v to 5.5 v ? package: 28-pin plastic ssop (ssop28-p-485-0.65-k) (product name : MSM7603-003gs-k) (product name : MSM7603b-003gs-k) e2u0064-18-82 this version: aug. 1998
? semiconductor MSM7603/7603b 2/20 block diagram MSM7603/7603b howling detector double talk detector power calculator adaptive fir filter (aff) nonClinear/ linear s/p att gain linear/ nonClinear p/s nonClinear/ linear s/p + + C att linear/ nonClinear p/s center clip rin rout sout sin rst v dd v ss pwdwn clock generator mode selector i/o controller sck sync nlp hcl adp att gc synco scko clkin pll hd m /a * for MSM7603b only
? semiconductor MSM7603/7603b 3/20 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nlp hcl adp sync sck v dd v ss rst pwdwn hd v dd [ m /a] * clkin v dd (pll) v ss (pll) v dd sout rout sin rin v ss nc nc[test] * v dd att scko gc synco v ss nc : no connect pin 28-pin plastic ssop * pins shown in brackets apply to MSM7603b.
? semiconductor MSM7603/7603b 4/20 pin descriptions pin symbol type description 1 nlp i 2 hcl i 3 adp i 4 sync i 5 sck i this is the control pin for the center clipping function to force the sout output to a minimum value when the sout signal is below C57 dbm0. effective for reducing low-level noise. "h": center clip on "l": center clip off this is the through mode control pin. when this pin is in the through mode the rin and sin data are output to rout and sout. at the same time, the coefficient of the adaptive fir filter is cleared. "h": through mode "l": normal mode (echo canceler operates) this is the aff coefficient control pin which stops updating the adaptive fir filter (aff) coefficient and sets it to a fixed value, when the pin is configured to be the coefficient fix mode. used when holding the aff coefficient which has been once converged. "h": coefficient fix mode "l": normal mode (coefficient update) this is the input pin for the sync signal for transmit/receive serial data. this pin uses the external sync or synco. inputs the pcm codec transmit/receive sync signal (8 khz). this is the clock input pin for transmit/receive serial data. it uses the external sck or the scko. input the pcm codec transmit/receive clock (64 to 2048 khz).
? semiconductor MSM7603/7603b 5/20 pin descriptions (continued) pin symbol type description 8 rst i 9 pwdwn i 10 hd i 12 clkin i 16 synco o this is the input pin for the reset signal. "l": reset mode "h": normal operation mode due to initialization, input signals are disabled for 100 m s after reset (after rst is returned from "l" to "h"). input the basic clock during the reset. output pins during the reset are in the following sates : high impedance: sout, rout not affected: synco, scko this is the power-down mode control pin for power down operation "l": power-down mode "h": normal operation mode during power-down mode, all input pins are disabled and output pins are in the following states : high impedance : sout, rout "l": synco, scko reset after the power-down mode is released. this pin controls the howling detect function that detects and cancels a howling generated during hands-free talking for acoustic system. this function is used to cancel acoustic echoes. "l": howling detector on "h": howling detector off this is the input pin for external input for the basic clock. input the basic clock (17.5 to 20 mhz). when the internal sync signal (synco, scko) is used, input the basic clock of 19.2 mhz. this is the output pin for the 8 khz sync signal for the pcm codec. connect to the sync pin and the pcm codec transmit/receive sync pin. leave open if using an external sync. 11 ( m /a) i used for MSM7603b only. this is the input pin for m -law pcm/a-law pcm interface select signal. "l": a-law pcm interface "h": m -law pcm interface for MSM7603, apply v dd . 13 v dd (pll) i this is the power supply pin for the pll circuit used for the basic clock. insert a 0.1 m f capacitor with excellent high frequency characteristics between v dd (pll) and v ss (pll). 14 v ss (pll) i this is the ground pin for the pll circuit used for the basic clock.
? semiconductor MSM7603/7603b 6/20 pin descriptions (continued) pin symbol type description 26 rout o 27 sout o 25 sin i 24 rin i 18 scko o 17 gc i 19 att i this is the pin for the input signal by which the gain controller for the rin input is controlled. the pin also controls rin input level and prevents howling. the gain controller adjusts the rin input level when it is C20 dbm0 or above. rin input levels from C20 to C11.5 dbm0 will be suppressed to C20 dbm0 in the attenuation range from 0 to 8.5 db. rin input levels above C11.5 dbm0 will always be attenuated by 8.5 db. "h": gain control on "l": gain control off "h" is recommended for performing echo cancellation. this is the output pin for the transmit clock signal (256 khz) for the pcm codec. connect to the sck pin and the pcm codec transmit/receive clock pin. leave open when using an external sck. this is the control pin for the att function which prevents howling by attenuators (att) for the rin input and sout output. if there is input only to rin, then the att for the sout output is activated. if there is no input to sin or there is input to both sin and rin, then the att for the rin input is activated. either the att for the rin output or the att for the sout is always activated in all cases, and the attenuation of att is 6 db. "h": att off "l": att on "l" is recommended for performing echo cancellation. this is the receive serial data input pin. input the pcm signal synchronized to sync and sck. data is read at the falling edge of sck. this is the transmit serial data input pin. input the pcm signal synchronized to sync and sck. data is read at the falling edge of sck. this is the output pin for receive serial data. outputs the pcm signal synchronized to sync and sck. this pin is in high impedance state during the absence of data output. this is the output pin for transmit serial data. outputs the pcm signal synchronized to sync and sck. this pin is in high impedance state during the absence of data output. 21 (test) o this pin is for MSM7603b only and not used. should be left open. in MSM7603 it is an nc pin.
? semiconductor MSM7603/7603b 7/20 absolute maximum ratings parameter power supply voltage input voltage power dissipation storage temperature symbol v dd v in p d t stg condition ta = 25?c rating C0.3 to + 7 C0.3 to v dd + 0.3 1 C55 to +150 unit v v w ?c recommended operating conditions parameter power supply voltage power supply voltage high level input voltage low level input voltage operating temperature symbol v dd v ss v ih v il ta condition min. 2.7 2.0 0 C40 unit v v v v ?c typ. 3.3 0 +25 max. 3.6 v dd 0.5 +85 (v dd = 2.7 v to 3.6 v) parameter power supply voltage power supply voltage high level input voltage low level input voltage operating temperature symbol v dd v ss v ih v il ta condition min. 4.5 2.4 0 C40 unit v v v v ?c typ. 5 0 +25 max. 5.5 v dd 0.8 +85 (v dd = 4.5 v to 5.5 v)
? semiconductor MSM7603/7603b 8/20 electrical characteristics dc characteristics (v dd = 2.7 v to 3.6 v, ta = C40?c to +85?c) parameter high level output voltage low level output voltage high level input current low level input current high level output leakage current low level output leakage current power supply current (operating) power supply current (standby) input capacitance output load capacitance symbol v oh v ol i ih i il i ozh i ozl i ddo i dds c i c load condition i oh = 40 m a i ol = 1.6 ma v ih = v dd v il = v ss v oh = v dd v ol = v ss pwdwn = "l" min. 2.2 0 C1 C1 typ. 0.1 C0.1 0.1 C0.1 30 0.5 max. v dd 0.4 1 1 50 1 15 20 unit v v m a m a m a m a ma ma pf pf (v dd = 4.5 v to 5.5 v, ta = C40?c to +85?c) parameter high level output voltage low level output voltage high level input current low level input current high level output leakage current low level output leakage current power supply current (operating) input capacitance output load capacitance power supply current (standby) symbol v oh v ol i ih i il i ozh i ozl i ddo i dds c i c load condition i oh = 40 m a i ol = 1.6 ma v ih = v dd v il = v ss v oh = v dd v ol = v ss pwdwn = "l" min. typ. 4.2 0 0.1 C10 C0.1 0.1 C10 C0.1 40 0.5 max. v dd 0.4 10 10 70 1 15 20 unit v v m a m a m a m a ma ma pf pf
? semiconductor MSM7603/7603b 9/20 echo canceler characteristics (refer to characteristics diagram) parameter echo attenuation cancelable echo delay time symbol l res t d condition r in = C10 dbm0 (5 khz band white noise) e. r. l. (echo return loss) = 6 db t d = 50 ms att, gc, nlp: off r in = C10 dbm0 (5 khz band white noise) e. r. l. = 6 db att, gc, nlp: off min. typ. max. unit 30db 55ms
? semiconductor MSM7603/7603b 10/20 ac characteristics parameter clock frequency when internal sync signal is not used clock cycle time when internal sync signal is not used clock duty ratio clock "h" level pulse width f c = 19.2 mhz clock "l" level pulse width f c = 19.2 mhz clock rise time clock fall time sync clock output time internal sync clock frequency internal sync clock output cycle time internal sync clock duty ratio internal sync signal output delay time internal sync signal period internal sync signal output width transmit/receive sync clock frequency transmit/receive sync clock cycle time transmit/receive sync clock duty ratio transmit/receive sync signal period sync timing sync signal width receive signal setup time receive data input time serial output delay time symbol f c t mck t dmc t mch t mcl t r t f t dcm f co t co t dco t dcc t cyo t wso f sck t sck t dsc t cyc t xs t sx t wsy t ds t id t sd t xd t wr min. 17.5 50.0 40 20.8 20.8 64 0.488 40 123 45 t sck 1 typ. 19.2 52.08 256 3.9 50 125 t co 50 125 7t sck max. 20.0 57.14 60 31.3 31.3 2048 15.6 60 t cyc -t sck min. 17.5 50.0 40 20.8 20.8 64 0.488 40 123 45 45 t sck 45 1 typ. 19.2 52.08 256 3.9 50 125 t co 50 125 7t sck max. 20.0 57.14 60 31.3 31.3 5 5 40 5 2048 15.6 60 t cyc -t sck 90 90 unit mhz ns ns ns ns ns ns ns khz m s % ns m s m s khz m s % m s ns ns m s ns m s ns ns m s v dd = 2.7 v to 3.6 v v dd = 4.5 v to 5.5 v (ta = C40?c to +85?c) reset start time t drs 5ns reset end time t dre 52ns processing operation start time t dit 100 100 m s reset signal input width power down start time power down end time t dps 111 15 ns t dpe ns control pin hold time ( rst )t dhr 20ns control pin setup time ( rst )t dsr 20ns 5 5 40 5 45 45 90 90 5 52 20 20 111 15 control pin setup time t dts 0ns 0 control pin hold time t dth 160 ns 160 reset pulse width immediately after power down t wpr 10ns 10 receive signal hold time t dh 45ns 45
? semiconductor MSM7603/7603b 11/20 timing diagram clock timing clkin t r t f t mch t mcl f c , t mck , t dmc scko t dcm scko synco t cyo t dco t dcc t dcc t wso f co , t co t dcm serial input timing sck sync sin rin msb 7 t cyc f sck , t sck t sx t xs t wsy t ds 654321 lsb 0 msb 7 t dsc t id t dh
? semiconductor MSM7603/7603b 12/20 serial output timing operation timing after reset power down timing t dps t dpe internal operation processing start power down pwdwn t wpr invalid rst sck sync sout rout msb 7 t cyc f sck , t sck t sx t xs t wsy t sd 654321 lsb 0 msb 7 t dsc high-z t xd t xd high-z t drs rst t wr t dre internal operaion processing start t dit reset initialization *reset timing can be asynchronous. * int is invalid durin g the shaded interval.
? semiconductor MSM7603/7603b 13/20 control pin load-in timing nlp, hcl, hd, att, adp, gc t dhr rst t wr t dsr sck sync sin msb 7 t cyc t id 654321 lsb 0 msb 7 rin nlp, hcl, hd, att, adp, gc t dth t dts
? semiconductor MSM7603/7603b 14/20 how to use the MSM7603/7603b the MSM7603/7603b cancels, based on the rin signal, the echo which returns to sin. connect the base signal to the r side and the echo-generated signal to the s side. connection methods according to echoes example 1: canceling acoustic echo (to handle acoustic echo from line input) + + C aff rout sin rin sout MSM7603 MSM7603b codec codec h line input acoustic echo example 2: canceling line echo (to handle line echo from microphone input) + + C aff rin sout rout sin MSM7603 MSM7603b codec codec h lin echo microphone input example 3: canceling of both acoustic and line echo (to handle both acoustic echo from line input and line echo from microphone input) sin rout codec h line input acoustic echo + + C aff rout sin MSM7603 MSM7603b + + C aff sout rin MSM7603 MSM7603b rin sout microphone input for acoustic echo line echo codec for line echo
? semiconductor MSM7603/7603b 15/20 echo canceler characteristics diagram (for m m m m m -law and a-law, and for reference only) 0 10 20 30 40 40 30 20 10 0 e. r. l. vs. echo attenuation echo attenuation [db] e. r. l. [db] measurement conditions : rin input = C10 dbm0 5 khz band white noise echo delay time t d = 50 ms att, gc, nlp = off power supply voltage 5 v 0 10 20 30 40 C50 C40 C30 C20 C10 0 rin input level vs. echo attenuation echo attenuation [db] rin input level [dbm0] measurement conditions : rin input: 5 khz band white noise echo delay time t d = 50 ms e.r.l. = 6 db att, gc, nlp = off power supply voltage 5 v 0 10 20 30 0 echo delay time vs. echo attenuation echo attenuation [db] echo dela y time [ ms ] 50 measurement conditions : rin input = C10 dbm 5 khz band white noise e.r.l. = 6 db att, gc, nlp = off power supply voltage 5 v 10 20 30 40 C10 note: above characteristics are for the msm7533 (v dd 5 v, m -law codec interface). for the msm7704 (v dd 3 v, m -law interface) the characteristics are basically the same except for input and output levels. refer to the pcm codec data sheet. msm7533 (for both transmit and receive) 0 dbm0 = 0.85 vrms = 0.8 dbm (600 w ) msm7704 (for transmit side) 0 dbm0 = 0.35 vrms = C6.9 dbm (600 w ) (for receive side) 0 dbm0 = 0.5 vrms = C3.8 dbm (600 w )
? semiconductor MSM7603/7603b 16/20 measurement system block diagram rin sout rout sin MSM7603b delay t d echo delay time att e. r. l. (echo return loss) power supply voltage 5 v rin sout l. p. f. 5 khz level meter white noise generator 2ch codec msm7533 MSM7603
? semiconductor MSM7603/7603b 17/20 application circuit bidirectional connection example microphone input c1 r1 speaker output dv r3 21 22 4 13 12 14 10 16 19 5 6 dv ain1 gsx1 aout1 dout1 din1 xsync rsync bclk a / m pdn chp ain2 gsx2 aout2 dout2 din2 v dd sgc ag dg 24 23 2 14 11 8 1 18 9 r2 r5 dv r7 r6 av + c9 c10 c11 c5 line input line output (ag) MSM7603/7603b for cancelation of acoustic echo MSM7603/7603b for cancelation of line echo dv r8 dv r4 25 26 4 5 16 18 9 8 12 6 20 28 dv pwdwn rst clk 27 24 1 2 19 17 11 13 7 15 23 3 10 14 sin rout sync sck synco scko rst pwdwn clkin v dd v dd v dd sout rin nlp hcl att gc v dd (p) v ss v ss v ss adp hd ( m / a ) v ss (p) sout rin nlp hcl att gc ( m / a ) v dd (p) v ss v ss v ss adp hd v ss (p) sin rout sync sck synco scko rst clkin v dd v dd v dd pwdwn 27 24 1 2 19 17 11 13 7 15 23 3 10 14 c4 c8 dv dv dv 25 26 4 5 16 18 9 8 12 6 20 28 dv + c6 c7 c2 c3 + r1=20 k w r2=20 k w r3=2.2 k w r4=10 k w r9=10 k w c1=1 m f c2=10 m f c3=0.1 m f c4=0.1 m f r5=20 k w r6=20 k w r7=2.2 k w r8=10 k w r10=10 k w c5=1 m f c6=10 m f c7=0.1 m f c8=0.1 m f c9=0.1 m f c10=10 m f c11=0.1 m f use the msm7704-01gs-vk as a pcm codec when v dd 3 v is used. the msm7533 is p in com p atible with the msm7704. 2ch codec msm7533vgs-k dv dv r9 r10 21 (test) 21 (test)
? semiconductor MSM7603/7603b 18/20 notes on use 1. set echo return loss (erl) to be attenuated. if the echo return loss is set to be amplified, the echo cannot be eliminated. refer to the characteristics diagram for e. r. l. vs. echo attenuation quantity. 2. set the level of the analog input so that the pcm codec does not overflow. 3. the recommended input level is C10 to C20 dbm0. refer to the characteristics diagram for the rin input level vs. echo attenuation quantity. 4. applying the tone signal to this echo canceler for long duration may decrease echo attenuation. when used with the hd pin "l" (howling detector on), this echo canceler may operate faultily if, while a signal is input to the rin pin, a tone signal with a higher level than the signal being input to rin is input to the sin pin. a signal should therefore be input either to the rin pin or to the sin pin. if, however, the tone signal is input to the sin pin while a signal is input to the rin pin, the adp, hd, or hcl pin must be set to "h". 5. for changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. perform a reset to make it converge. if the state of the echo path changes after a reset, convergence may again be difficult. in cases such as a change in the echo path, perform a reset each time. 6. when turning the power on, set the pwdwn pin to "1" and input the basic clock simultaneously with power on. if the device is put into power down mode immediately after power on, be sure to input 10 or more clocks of the basic clock before setting to the power down mode. 7. after power on, be sure to reset the device. 8. after the power down mode is released (when pwdwn pin is changed to a "1" from a "0"), be sure to reset the device. 9. if this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 db.
? semiconductor MSM7603/7603b 19/20 explanation of terms attenuating function : this function prevents howling and controls the noise level with the attenuator for the rin input and sout output. refer to the explanation of pins (att pin). echo attenuation : if there is talking (input only to rin) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. echo attenuation = (sout level during through mode operation) C (sout level during echo canceler operation) [db] echo delay time : this is the time from when the signal is output from rout until it returns to sin as an echo. acoustic echo : when using a hands-free phone, for example, the signal output from the speaker echoes and is input again to the microphone. the return signal is referred to as acoustic echo. telephone line echo : this is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. gain control function : this function prevents howling and controls the sound level by with a gain controller for the rin input. refer to the explanation of pins (gc pin). center clipping function : this function forces the sout output to a minimum value when the signal is below C57 dbm0. refer to the explanation of pins (nlp pin). double talk detection : double talk refers to a state in which the sin and rin signals are input simultaneously. in a double talk state, a signal other than the echo signal which is to be canceled can be input to the sin input, resulting in malfunction. the double talk detector prevents such malfunction of the canceler. howling detection : this is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands-free talking. howling not only interferes with talking, but can also cause malfunction of the echo canceler. the howling detector prevents such malfunction and howling. echo return loss (erl) : when the signal output from rout returns to sin as an echo, erl refers to how much loss there is in the signal level during rout. erl = (rout level) C (sin level of the rout signal which returns as an echo) [db] if erl is positive (rout > sin), acts as an attenuator. if erl is negative (rout < sin), acts as an amplifier. phs : personal handyphone system
? semiconductor MSM7603/7603b 20/20 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop28-p-485-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.39 typ. mirror finish

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